The present invention relates in general to the improved use of Field Effect Transistors as a voltage controlled impedance and their application in circuits that require dynamic analog information signal modification where low distortion is a primary metric of signal quality. Specifically, it focuses on significantly improving FET linearity by reducing channel impedance variations that result from information signal variations and are not associated with changes in the Gate controlling voltage source.
Field Effect Transistors have been widely used in analog circuit applications as a means of dynamically controlling analog information signal parameters such as frequency, gain, phase, or bandwidth. The application of FET technology in these specific types of circuit designs provides distinct advantages over alternative bipolar technology solutions. These advantages are predominantly in the area of achieving high linearity (low distortion), high control input impedance, or low reactive parasitic impedances. This is due to the nature of the FET voltage current characteristic equations that are a result of semiconductor physics and fabrication processes.
As mentioned, there are numerous circuit applications for FET""s. The most common applications relate to circuits that require a voltage controlled impedance to change the amplitude of the analog information signal being controlled. The voltage controlled impedance functionality of these devices is also widely used to dynamically change other signal parameters such as (but not limited to) frequency, phase, or bandwidth. To achieve high linearity and therefore low distortion in all of these types of applications, the FET channel impedance must electrically operate as close as possible to an equivalent value resistance for any instantaneous value of Gate-to-Source voltage in the ohmic region of the characteristic V/I curve. Although FET""s have a more linear V/I curve than their bipolar transistor counterparts when used in small signal applications, the V/I curve of FET""s is still inherently non-linear. To illustrate this, the first-order effect, instantaneous small signal V/I equation of an N-Channel Depletion Mode JFET operating in the ohmic region is set forth in equation (1) below as stated in Hayt and Neudeck, Electronic Circuit Analysis and Design 2nd Edition, p.63, 1984.                    Id        =                  D          ⁡                      (                                                            [                                      Vgs                    -                    Vp                                    ]                                *                Vds                            -                                                Vds                  2                                2                                      )                                              (        1        )            
In the above equation, D is a constant based on semiconductor physics, manufacturing process parameters, and physical dimensions. Vp is the FET""s specified xe2x80x9cpinch-ofxe2x80x9d voltage, Vgs is the instantaneous channel impedance controlling voltage measured between the Gate-to-Source terminals, and Vds is the instantaneous voltage value measured between the Drain and Source terminals and is the analog information signal. The inherent non-linearity of this device results from the       Vds    2    2
term in the equation. Other types of FET""s such as P-Channel Depletion Mode, N-Channel Enhancement Mode, or P-Channel Enhancement Mode have similar equations and differ only in sign and the value of their associated constants. This term within the equation implies that higher degrees of linearity can be achieved by reducing the amplitude of the analog information signal (Vds) which is a standard application technique. Using this technique however sacrifices Signal-to-Noise which is another common signal-quality figure of merit for circuits that strive to achieve low distortion.
Another means of improving linearity and thus reducing distortion is to reduce the effect of the non-linear term shown above by connecting fixed resistances (linear devices) in series and/or in parallel with the FET channel impedance (e.g. Gingrich et al., U.S. Pat No. 5,175,508, Dec. 29, 1992). Although this approach effectively improves the linearity by reducing the net effect of the non-linear term, it does so at the sacrifice of the dynamic impedance range provided by the FET. In other words, this approach seeks to mask the non-linear term but does not cancel the non-linear term.
FET channel impedance linearity can also be improved in the manufacturing process (e.g. Green, Jr., U.S. Pat. No. 5,266,506, Nov. 30th, 1993). Although this may be an effective way to achieve the high linearity goal, it involves highly controlled state-of-the-art semiconductor manufacturing processes which usually results in a significantly higher component cost. In spite of this approach""s degree of improvement in FET linearity, if a specific device""s characteristic equation can be shown in a mathematically similar form to equation (1), then further significant improvements in linearity could be achieved through the application of this invention. In addition, the utilization of this invention may indeed achieve greater improvements in linearity than that of Green, Jr. allowing cost effective semiconductor manufacturing processes to be used while achieving the same highly linear results.
The main objective of this invention is to significantly improve FET channel impedance linearity in semiconductor devices and analog circuit applications that require low distortion in analog information signal quality without sacrificing other performance advantages that FET""s can provide such as (but not limited to) Signal-to-Noise or Dynamic Range. Through the application of this invention, the claimed improvement is realized for FET semiconductor devices and circuit applications where utilization of the FET as a voltage controlled impedance is the primary function and therefore designed to operate in the ohmic region of the characteristic small-signal V/I curve.
Another objective of this invention is to provide an improvement of FET channel impedance linearity that is not dependent upon the electrical specifications of the specific FET device or semiconductor manufacturing process being used Achievement of this objective enables the use of cost-effective components or semiconductor manufacturing processes to achieve a higher degree of information signal quality performance than would otherwise be achievable at a comparable cost.
The present invention accomplishes these objectives through the implementation of a mathematical derivation that cancels the nonlinear term contained in the characteristic voltage-to-current equation (1) for FET""s operating in the ohmic region of their small-signal V/I curve. This characteristic equation models the small-signal voltage-to current behavior of an FET operating in the ohmic region. This equation does not model the comparatively negligible second-order effects resulting from semiconductor junction and terminal parasitic impedances. Specifically, the implementation of the above mentioned derivation requires the application of a specific transfer function to the analog information signal across the Drain-to-Source terminals (Vds). The output of this transfer function is summed with the instantaneous value of the Gate controlling voltage (Vg) to produce a voltage that is applied across the Gate-to Source terminals (Vgs). This process of modifying the value of Vgs cancels the non-linear FET channel impedance variations that result from the varying analog information signal across the Drain-to-Source terminals (Vds).